tag:blogger.com,1999:blog-5244802588533844551.post3919826541395700242..comments2023-03-30T22:21:48.385-07:00Comments on ionipti: ISE 11.1 stability issuesnachumkhttp://www.blogger.com/profile/15062996095552781936noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-5244802588533844551.post-8892627489252528782009-07-06T14:10:19.181-07:002009-07-06T14:10:19.181-07:00What I can suggest is to open a WebCase or post th...What I can suggest is to open a WebCase or post the issue on Xilinx forum. <br /> I've done it many times and can attest that Xilinx does fix the problems.Evgenihttp://outputlogic.comnoreply@blogger.comtag:blogger.com,1999:blog-5244802588533844551.post-6588769992149150072009-05-30T04:09:23.694-07:002009-05-30T04:09:23.694-07:00Hi anon,
I'm not sure what directory you are refer...Hi anon,<br />I'm not sure what directory you are referring to. ISE 11.1 projects don't have an implementation folder from what I've seen. I am writing in Verilog for this application and perhaps the compilation system is different. Thanx for reading,<br />nachumnachumkhttps://www.blogger.com/profile/15062996095552781936noreply@blogger.comtag:blogger.com,1999:blog-5244802588533844551.post-46474041763201009952009-05-30T02:59:38.244-07:002009-05-30T02:59:38.244-07:00Hi,
There is a better way to synthesize only the...Hi, <br /><br />There is a better way to synthesize only the modified files. Go into the "implementation/" directory and delete both the library which is named after your VHDL source file module AND the filename in the cache library. After that, if you click on 'run' it will not syntheize the world again.Anonymousnoreply@blogger.com