tag:blogger.com,1999:blog-5244802588533844551.post7772455574802114980..comments2023-03-30T22:21:48.385-07:00Comments on ionipti: SystemVerilog variable argument display (printf)nachumkhttp://www.blogger.com/profile/15062996095552781936noreply@blogger.comBlogger1125tag:blogger.com,1999:blog-5244802588533844551.post-46107825046858081062021-06-16T17:25:00.518-07:002021-06-16T17:25:00.518-07:00It ain't pretty but 10 years later, this still...It ain't pretty but 10 years later, this still seems to be the best solution to the need for varargs in system verilog or PLI/VPI/DPI. Runs in VCS. Just one issue- the code below throws compile error on 'else', presumably because the macro expands to more than 1 statement (?):<br />if (test)<br /> `DEBUG_PRINT("took if");<br />else<br /> `DEBUG_PRINT("took else");<br />Anonymoushttps://www.blogger.com/profile/10834294632098675030noreply@blogger.com