SystemVerilog wish list and SV2012

So I've read up a bit on the newest SystemVerilog standard, SV 2012. There are a few simple things I like:
You can now call new from another object.
In SV 2009:
class cl_base;
...
endclass
class cl_ext extends cl_base;
...
endclass

So now I want to instantiate a cl_ext and point to it with a cl_base pointer.
Some people will code this verbosely:
cl_base cl_b_inst;
cl_ext cl_e_inst = new();
cl_b_inst = cl_e_inst;

I have always resolved this using another method in cl_ext:
static function cl_ext create();
cl_ext t;
t = new();
return t;
endfunction

This way allows me to do this:
cl_base cl_b_inst = cl_ext::create();

But now, with SV 2012, you can directly call new:
cl_base cl_b_inst = cl_ext::new();

Now onto the next improvement that I am excited about: Multiple Inheritance! The new SV 2012 now supports multiple inheritance by using an interface class. Don't know how that works as I haven't used it yet.

Now, onto my wishlist:
Allow constant functions to call system tasks. For example:
localparam blah = $urandom();
That'd help for some of my randomized teesting

Variable length arguments would be nice, make it easier to create a new display function with added parameters.

Pass signals directly into a class, but of course... that will never happen. For now you just have to wrap signals in an interface to keep them handy for a class to use.

Allow multi dimensional arrays with both types and widths:
wire [count - :0] int my_integers;

Allow for seamless multidimensional array flipping:
wire [a_count - 1:0] [b_count - 1:0] wires_a_by_b;
for(int bi = 0; bi < b_count; b++)
  b_reduce[bi] = $flip(wires_a_by_b)[b];

or something like that... This might work with a function, but I do believe that SystemVerilog still doesn't support unconstrained types for a function.

Generate statements in a class:
SV supports parameters in a class, but it won't allow for generate statements in a class. This is both unexpected, and annoying. If parameters are allowed appear identical to parameters for a module or interface, then they should behave more or less the same!

Wildcard connections of parameters. It would've helped me today.

I know there is something I want having to do with clocking blocks... One second, I have to find it...
So I want some indication of when a clocking block updates a signal. See forum post for more information.

Here's the link to my question:
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=20576

Now onto Cadence:
PLEASE allow modports inside generate statements!

I know there is more, but I can't recall now sitting in front of the TV.

Xilinx KC705 PCI Express on Ivy Bridge (i7 3rd Gen)

I am doing work on a KC705 evaluation board from Xilinx. This chip (Kintex 7) uses the 7 Series Integrated Block for PCI Express. I am running this on a Gigabyte GA-Z77X-UP5 TH board. I have run into a brick wall trying to get this Xilinx board to work on this Gigabyte motherboard. Luckily, there is a note from Xilinx about this:
http://www.xilinx.com/support/answers/51135.htm

In short, there is a workaround. Check out this page, which tells you to set the TX_RXDETECT_REF signal to 3'b011 instead of the default. The Answer Record also explains that this is due to an errata on Ivy Bridge cores. It points to a web page by Intel and indicates that it is errata BV56.
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf

I don't understand the errata, but I can attest to the fact that this fixes the problem. The KC705 is now successfully detected on this motherboard.

UPDATE: If you take a look at
http://www.xilinx.com/support/documentation/boards_and_kits/kc705_PCIe_pdf_xtp197_14.2.pdf
you can see that by setting the Bitstream Configuration, and by adding an emcclk you can accomplish a PCIe compliant FPGA load-time. This method doesn't need a soft-reboot to properly enumerate the bus.

See note above, kept for accuracy:
Even with this success, there are still some failures... For example, the load time for the FPGA configuration is too long. This means that I have to do a soft-reboot after a hard reboot to get the PCIe link to work. Xilinx has created a method to solve this, but I have yet to figure it out. It is called Tandem PROM and Tandem PCIe. It is supposed to quickly load the PCIe portion, negotiate the link, and then load the rest.

For now, I'm just doing a soft-reboot (ctrl-alt-del).

finding combinational loops in ncsim

There may be better ways of doing this... but here was my way:

You are running gate level or rtl simulations, and the simulation gets stuck. Yup, what do you do?

Simple answer is not to have combinational loops. If you do, perhaps you've done something wrong. If you must have combinational loops, or you are debugging someone else's code, then here's the way I found the loop path. This is especially useful when you are unfamiliar with the code, and the code spans many files and many processes.

Use NCSIM's built in "Create Force" option. I just debugged a combinational loop, and this worked like clockwork. I could follow the whole loop, and figure out which branches were being taken by selectively forcing signals. When a force caused the simulation to continue, that signal is part of the loop. If the force had no effect, that signal is not part of the loop. This worked well for me as it didn't take too long to get the simulator stuck. If it takes a long time before it gets stuck this may not work well as it requires continuously restarting the simulation to test each sequential branch.

VS 2005 convert to VS 2010 - property pages

A client sent me their Visual Studio 2005 project. I have Visual Studio 2010 Express. I opened the project, and it offered to convert it. It failed miserably. First thing is, it couldn't handle the x64 configurations. So I opened the VS 2005 vcproj file, and I removed the x64 configurations. Yay!

It now opens the project, (reporting that conversion passed without errors). Except that it is lying. The property pages have converted as pretty much empty files. It has the XML header, but all of the property pages are empty.

Long story short, go to the command line, and use vcupdate on the original vcproj file. One problem I noticed was the SolutionDir wasn't available as you can't run vcupdate on an sln file. So in the command prompt, type:

set SolutionDir=(path of the project)

Then run vcupgrade on the vcproj file. Make sure the path is a fixed path and not relative to the vcproj file.

That does it, the property pages get converted properly!

Xilinx Zynq - harder to implement than one would hope

So I get a new Zynq ZC702 development board, and I'm tasked with making it work. I got the new ISE 14.2 development tools from Xilinx. Here are some things you might want to know if you encounter the same board.

The FPGA logic is the PL (Programming Logic), and the A9 subsystem is the PS (Processor System). Don't attempt to use Impact to burn anything! The burning is all done through an application called zynq_flash.exe.

Do not use Project Navigator to build this FPGA bitstream! Even if you wanted to, which I did, you will find that ngdbuild crashes most of the time (when using the embedded A9) in this flow. Use PlanAhead. It is the new recommended flow from Xilinx. Its also a surprisingly good flow.

The flow I'm using is:
Create a project in XPS. Set up everything that you need for interfacing to the PL there.
Export the project for the SDK, it's an option in XPS. Don't generate the bitstream. Don't launch the SDK.
Create a new project in PlanAhead. Import the .xmp project that you created in XPS. Right click on the embedded processor to create a stub file. Add your source files, and build the rest of the project there.
Generate a bitstream.
Open SDK. Create a new hardware platform specification. Browse for the .XML file under the XPS project in the SDK export folder. Choose the bitstream that was built by PlanAhead. If you have a .bmm file, then use it.
Create a new BSP based on this platform.
Create a new C project and choose Zynq FSBL. You need the FSBL (First Stage Bootloader) to burn the FPGA. It is also needed by the A9 to boot up. Select the platform that you created for the FSBL.
Create a project for your application based on the platform you created.

To burn, right click on the application, and choose to create image. It will automatically add the FSBL, bitstream, and application. To burn the new .mcs file, use the Xilinx tools menu, and burn flash. This is using the zynq_flah applicaion.

Some caveats, I have seen zynq_flash claim to burn even when it doesn't. If the erase step doesn't take at least a few seconds (more like 30+), then it's not working. I have never seen the verify option work at all. If it isn't burning, then turn off the board for a few minutes, and try again.

That's about it.

Libero SOC and IO constraints

A rule that I have always kept to is : Keep design source files as text! A  while back I had the misfortune of using ATEasy. Back then all ATEasy projects were binary, and the sources were stored in the project. This made it very hard to compare versions or to store the sources in revision control. This was bad back then. Even then, ATEasy became aware of the problem and added an option to store project files as text.
Getting back to Microsemi / Actel... The newest version of the tool no longer allows out to use a PDC file to store IO constraints. You must maintain the constraints from within Designer. This is unpleasant to say the least. The constraints are held in the Designer project file. The project file is not only binary, but it is updated on every run.
You can of course import a PDC file, but don't try and change the IOs around without first opening the tool to unassign all IOs from the Designer database. Otherwise you'll get errors about conflicting IO assignments.
Please fix this!

SystemVerilog variable argument display (printf)

Ah, the joy of perfection.

Any C / C++ programmers now programming in SystemVerilog must feel pretty constrained by language limitations. One of the frustrations that I felt today was the lack of variable argument (varargs) support. I wanted to be able to overload a print function (ie write my own $display) and selectively print or not print based on debug levels or the like. Actually... what I wanted was to store all the debug prints between runs, and only print them in the case of an error, but that's besides the point. I needed a way to overload the $display function.

Here is what I've finally come up with: (be ready, it's wild)

$display("Print with no arguments");

$display("Print with 1 argument %t", $time());

$display("Print with 2 arguments %t, %d", $time(), 5);

$display("Print with 3 arguments %t, %d, %s", $time(), 5, "debug");

etc...

I wanted this to become:

DEBUG_PRINT("Print with no arguments");

DEBUG_PRINT("Print with 1 argument %t", $time());

DEBUG_PRINT("Print with 2 arguments %t, %d", $time(), 5);

DEBUG_PRINT("Print with 3 arguments %t, %d, %s", $time(), 5, "debug");

etc...

Is it possible??

Yes! (at least until someone points out a flaw)

The solution is based on macros that can have variable number of arguments, and the preprocessor allowing ifdef on substituted strings

function void my_debug(string s);

...

endfunction

`define DELIM

`define DEBUG_PRINT(p0, p1=ELIM, p2=ELIM, p3=ELIM, p4=ELIM, p5=ELIM) \

`ifdef D``p1 \

my_debug($psprintf(p0)); \

`else \

`ifdef D``p2 \

my_debug($psprintf(p0, p1)); \

`else \

`ifdef D``p3 \

my_debug($psprintf(p0, p1, p2)); \

`else \

`ifdef D``p4 \

my_debug($psprintf(p0, p1, p2, p3)); \

`else \

`ifdef D``p5 \

my_debug($psprintf(p0, p1, p2, p3, p4)); \

`else \

my_debug($psprintf(p0, p1, p2, p3, p4, p5)); \

`endif \

`endif \

`endif \

`endif \

`endif

This solution works on Cadence Incisive 12.1

Tell me what you think of this solution,

Nachum