SystemVerilog array of objects initialization

So I'm updating one of my testbenches and I want to create an array of objects. For example:
A_class a_instance[num];

I also want to pass these objects to modules and other created objects.

B_class b_instance = new (a_instance[0]);
C_mod c_modinst (.a(a_instance[0]));

The biggest issue is that a_instance isn't yet initialized.

If you try and initialize with

initial begin
for(genvar i = 0; i < num; i++) a_instance[i] = new();
end

This won't work. Has something to do with object and module creation running before initial lines. The initial statement is too late, a null object was passed in and that's what the object and modules will have.

When I was passing a non array, it would work b/c the declaration included an assignment:
A_class a_instance = new();
but you can't call new on an array.

Here's what appears to work:
A_class a_instance = '{num{A_class::create()}};

This surprised me as I am using replication. It looks like each instance points to its own object. This resolves the problem. Now on the declaration line, I can initialize the objects. Passing the objects around works well now.

Update from Idan's comment:
A_class a_instance = '{default:A_class::create()};

This uses the default syntax for filling in an array. Much nicer than the replication mechanism.

About the create function: SystemVerilog doesn't allow you to call new on a class type so I use a create function instead:

class a;
 function new();
  $display("creating a");
 endfunction
 static function a create();
  class a_inst;
  a_inst = new();
  return a_inst;
 endfunction
endclass

I believe others refer to this as a factory create function or something like that. Now creating a is as easy as calling a::create().

Installing rdesktop with user privileges (Red Hat EL 5.5)

Recently I came across a challenge of installing remote desktop without root privileges. Here is the information. Kudos to: http://www.nordugrid.org/documents/rpm_for_everybody.html for showing me how to do this.

In my home directory I performed these steps:
# make rpm database
mkdir rpmdb
rpmdb --initdb --dbpath ~/rpmdb/
# prepare folders
mkdir -p rpmtop/RPMS/i386
mkdir rpmtop/SRPMS
mkdir rpmtop/SOURCES
mkdir rpmtop/BUILD
mkdir rpmtop/SPECS
mkdir rpmtmp
echo `%_dbpath /home//rpmdb' | cat >> ~/.rpmmacros 
echo '%_topdir /home//rpmtop' | cat >> ~/.rpmmacros 
echo '%_tmppath /home//rpmtmp' | cat >> ~/.rpmmacros 
# copy system installed rpm list (must do this to meet dependency requirements of desired apps)
cp /var/lib/rpm/* rpmdb/.
# build rdesktop
rpmbuild --rebuild rdesktop-1.6.0-3.src.rpm
# install rdesktop
rpm -ivh rpmtop/RPMS/x86_64/rdesktop-1.6.0-3.x86_64.rpm
# since rdesktop uses keymaps by default from /usr/local, and since rdesktop isn't installed there, we will cheat by creating a link to 'user' available keymaps
ln -s usr/share/rdesktop/ ~/.rdesktop

This will give you:

/usr/bin/rdesktop

which works wonderfully well for connecting to remote windows systems.

Xilinx ISE (Project Navigator) x64 (64 bit) on Windows 8

Quick tip for those frustrated by file dialog crashes in Xilinx ISE x64 on Windows 8.

Rename libPortability.dll to libPortability.dll.orig, and copy libPortabilityNOSH.dll to libPortability.dll.

Do this in:

C:\Xilinx\14.5\ISE_DS\ISE\lib\nt64

C:\Xilinx\14.5\ISE_DS\common\lib\nt64 (copy dll from first location)

This turns off SmartHeap.

This will fix ISE and iMPACT crashes on file dialogs.

This information was found from another thread, thank you howardp from Xilinx in this thread:

http://forums.xilinx.com/xlnx/board/crawl_message?board.id=DEENBD&message.id=1732

This doesn't resolve Vivado or PlanAhead issues. This only helps for ISE and iMPACT on Windows 8 x64.

SystemVerilog wish list and SV2012

So I've read up a bit on the newest SystemVerilog standard, SV 2012. There are a few simple things I like:
You can now call new from another object.
In SV 2009:
class cl_base;
...
endclass
class cl_ext extends cl_base;
...
endclass

So now I want to instantiate a cl_ext and point to it with a cl_base pointer.
Some people will code this verbosely:
cl_base cl_b_inst;
cl_ext cl_e_inst = new();
cl_b_inst = cl_e_inst;

I have always resolved this using another method in cl_ext:
static function cl_ext create();
cl_ext t;
t = new();
return t;
endfunction

This way allows me to do this:
cl_base cl_b_inst = cl_ext::create();

But now, with SV 2012, you can directly call new:
cl_base cl_b_inst = cl_ext::new();

Now onto the next improvement that I am excited about: Multiple Inheritance! The new SV 2012 now supports multiple inheritance by using an interface class. Don't know how that works as I haven't used it yet.

Now, onto my wishlist:
Allow constant functions to call system tasks. For example:
localparam blah = $urandom();
That'd help for some of my randomized teesting

Variable length arguments would be nice, make it easier to create a new display function with added parameters.

Pass signals directly into a class, but of course... that will never happen. For now you just have to wrap signals in an interface to keep them handy for a class to use.

Allow multi dimensional arrays with both types and widths:
wire [count - :0] int my_integers;

Allow for seamless multidimensional array flipping:
wire [a_count - 1:0] [b_count - 1:0] wires_a_by_b;
for(int bi = 0; bi < b_count; b++)
  b_reduce[bi] = $flip(wires_a_by_b)[b];

or something like that... This might work with a function, but I do believe that SystemVerilog still doesn't support unconstrained types for a function.

Generate statements in a class:
SV supports parameters in a class, but it won't allow for generate statements in a class. This is both unexpected, and annoying. If parameters are allowed appear identical to parameters for a module or interface, then they should behave more or less the same!

Wildcard connections of parameters. It would've helped me today.

I know there is something I want having to do with clocking blocks... One second, I have to find it...
So I want some indication of when a clocking block updates a signal. See forum post for more information.

Here's the link to my question:
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=20576

Now onto Cadence:
PLEASE allow modports inside generate statements!

I know there is more, but I can't recall now sitting in front of the TV.

Xilinx KC705 PCI Express on Ivy Bridge (i7 3rd Gen)

I am doing work on a KC705 evaluation board from Xilinx. This chip (Kintex 7) uses the 7 Series Integrated Block for PCI Express. I am running this on a Gigabyte GA-Z77X-UP5 TH board. I have run into a brick wall trying to get this Xilinx board to work on this Gigabyte motherboard. Luckily, there is a note from Xilinx about this:
http://www.xilinx.com/support/answers/51135.htm

In short, there is a workaround. Check out this page, which tells you to set the TX_RXDETECT_REF signal to 3'b011 instead of the default. The Answer Record also explains that this is due to an errata on Ivy Bridge cores. It points to a web page by Intel and indicates that it is errata BV56.
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf

I don't understand the errata, but I can attest to the fact that this fixes the problem. The KC705 is now successfully detected on this motherboard.

UPDATE: If you take a look at
http://www.xilinx.com/support/documentation/boards_and_kits/kc705_PCIe_pdf_xtp197_14.2.pdf
you can see that by setting the Bitstream Configuration, and by adding an emcclk you can accomplish a PCIe compliant FPGA load-time. This method doesn't need a soft-reboot to properly enumerate the bus.

See note above, kept for accuracy:
Even with this success, there are still some failures... For example, the load time for the FPGA configuration is too long. This means that I have to do a soft-reboot after a hard reboot to get the PCIe link to work. Xilinx has created a method to solve this, but I have yet to figure it out. It is called Tandem PROM and Tandem PCIe. It is supposed to quickly load the PCIe portion, negotiate the link, and then load the rest.

For now, I'm just doing a soft-reboot (ctrl-alt-del).

finding combinational loops in ncsim

There may be better ways of doing this... but here was my way:

You are running gate level or rtl simulations, and the simulation gets stuck. Yup, what do you do?

Simple answer is not to have combinational loops. If you do, perhaps you've done something wrong. If you must have combinational loops, or you are debugging someone else's code, then here's the way I found the loop path. This is especially useful when you are unfamiliar with the code, and the code spans many files and many processes.

Use NCSIM's built in "Create Force" option. I just debugged a combinational loop, and this worked like clockwork. I could follow the whole loop, and figure out which branches were being taken by selectively forcing signals. When a force caused the simulation to continue, that signal is part of the loop. If the force had no effect, that signal is not part of the loop. This worked well for me as it didn't take too long to get the simulator stuck. If it takes a long time before it gets stuck this may not work well as it requires continuously restarting the simulation to test each sequential branch.

VS 2005 convert to VS 2010 - property pages

A client sent me their Visual Studio 2005 project. I have Visual Studio 2010 Express. I opened the project, and it offered to convert it. It failed miserably. First thing is, it couldn't handle the x64 configurations. So I opened the VS 2005 vcproj file, and I removed the x64 configurations. Yay!

It now opens the project, (reporting that conversion passed without errors). Except that it is lying. The property pages have converted as pretty much empty files. It has the XML header, but all of the property pages are empty.

Long story short, go to the command line, and use vcupdate on the original vcproj file. One problem I noticed was the SolutionDir wasn't available as you can't run vcupdate on an sln file. So in the command prompt, type:

set SolutionDir=(path of the project)

Then run vcupgrade on the vcproj file. Make sure the path is a fixed path and not relative to the vcproj file.

That does it, the property pages get converted properly!