I don't like indentation for Verilog (or VHDL), so I've decided to try and fix it. The best way to do that would be to understand how it works. I opened the ftplugin file verilog.vim and started reading. That's the why. Hopefully someone else will get something from the few useful gems I've gleaned.
DISCLAIMER: I do not know that I'm even understanding this correctly. I'm reading and gleaning as best as I can. It's strange code. Comments with corrections are appreciated.
s: (s colon) - script variables
a: (a colon) - argument variables
b: (b colon) - buffer variables
g: (g colon) - global variables
v: (v colon) - ... maybe it's the visual mode variables
=~ (equal tilda) - type match
: (colon) - type of dictionary or list
%( (percent open-parenthesis) - start of match that doesn't store in back-reference variables
%5c, %<5c, %>5c, %5l, %<5l, %>5l (percent number c), (percent number less-than c), (percent number greater-than c), (percent number l), (percent number less-than l), (percent number greater-than l) - search modifier to find at specific column (c) or line (l) with optional less-than or greater-than specified column or line.
Look at this guy's page, finally stumbled onto it:
and this page:
and this one too: