Monday, July 6, 2009

ISE 11.2 and Partitions

Recently I thought to speed up my FPGA compilation times. One method of doing this is by using "Partitions." The idea behind a partition is that you mark a module or hierarchy of modules as a partition and that partition gets processed once and that's it. Unless of course you modify the partition in which case it is synthesized / mapped / placed and routed again.

Wouldn't it be nice if things worked as they were supposed to?

So partitions in ISE are going to be removed in version 12.1 and they will then only be available in PlanAhead. This means that Xilinx won't fix any of the many wonderful bugs in their partition implementation.

Two bugs that I've experienced with partitions:
1. Modify a source file that causes ISE's automated uninitiated parsing of source files to fail and all partition information may be removed. That depends on how badly the parsing failed. This sucks as ISE will parse your source files as soon as you set focus back onto ISE, and of course you may not be done editing your source files at that moment. (It should be noted that I use an external editor for my source files.)
2. INTERNAL_ERROR:Xst:cmain.c:3446: -
I don't know what this error is but it won't let my partitions work...

I've of course removed all partitions from the design.

hoping you have better experience with partitions

Thursday, July 2, 2009

Using synchronous resets - delay them!

When I first started writing FPGAs some years back I was always shown how to use asynchronous resets. This reset line would have it's timing blocked, and it would be used throughout the FPGA. I have now become accustomed to using synchronous resets, and the first very obvious mistake I made was using a single reset line synchronously. This causes a huge and wasteful fanout. Register the reset line as it goes into different modules and you'll save yourself time when it comes to routing. It'll cost a few extra flip flops, but it's worth it. If your design can't deal with different modules coming out of reset at different times, then perhaps its time to rethink your design.