Why does SystemVerilog need so many constructs? There is too much overlap.
An interface could almost be a module if you don't need any module instantiations inside. A task or function can exist in classes, interfaces, or modules. Which should they exist in? Call a task from a module or use an interface to control the IOs of the interface? Output an inherited class from the module and call the class' tasks? Use a typed or untyped mailbox? How about using nested classes? Should they be nested or just in a hidden package? Classes in packages or classes at the top-level with include files? What sounds right to you?
