So I was analyzing my design today and I happened upon another metastability mistake. I built this circuit:
I wanted to synchronize an external signal, but only when enabled. There was a good reason to do this, but I didn't want to risk metastability. I figured that the second flop solved the issue. What I didn't take into account was the feedback path of the first flop when the enable was low. It was theoretically possible that the first flop would oscillate metastable, even if only for l additional clock. Under most conditions you would assume that a single mux would be minor when compared to the full period of the clock and therefore it wouldn't be a problem. But it's not just an additional mux, it is also two wire paths instead of 1. That means that layout tools with a max wire path distance would now be doubled as there is a path from the q to the mux input, and from the mux output to the d. A nice solution was replacing the mux and enable with a clock gate enabled by the enable. At least this way you don't have to worry about the feedback path.
Be sure to balance the clocks!