SystemVerilog wish list and SV2012

So I've read up a bit on the newest SystemVerilog standard, SV 2012. There are a few simple things I like:
You can now call new from another object.
In SV 2009:
class cl_base;
...
endclass
class cl_ext extends cl_base;
...
endclass

So now I want to instantiate a cl_ext and point to it with a cl_base pointer.
Some people will code this verbosely:
cl_base cl_b_inst;
cl_ext cl_e_inst = new();
cl_b_inst = cl_e_inst;

I have always resolved this using another method in cl_ext:
static function cl_ext create();
cl_ext t;
t = new();
return t;
endfunction

This way allows me to do this:
cl_base cl_b_inst = cl_ext::create();

But now, with SV 2012, you can directly call new:
cl_base cl_b_inst = cl_ext::new();

Now onto the next improvement that I am excited about: Multiple Inheritance! The new SV 2012 now supports multiple inheritance by using an interface class. Don't know how that works as I haven't used it yet.

Now, onto my wishlist:
Allow constant functions to call system tasks. For example:
localparam blah = $urandom();
That'd help for some of my randomized teesting

Variable length arguments would be nice, make it easier to create a new display function with added parameters.

Pass signals directly into a class, but of course... that will never happen. For now you just have to wrap signals in an interface to keep them handy for a class to use.

Allow multi dimensional arrays with both types and widths:
wire [count - :0] int my_integers;

Allow for seamless multidimensional array flipping:
wire [a_count - 1:0] [b_count - 1:0] wires_a_by_b;
for(int bi = 0; bi < b_count; b++)
  b_reduce[bi] = $flip(wires_a_by_b)[b];

or something like that... This might work with a function, but I do believe that SystemVerilog still doesn't support unconstrained types for a function.

Generate statements in a class:
SV supports parameters in a class, but it won't allow for generate statements in a class. This is both unexpected, and annoying. If parameters are allowed appear identical to parameters for a module or interface, then they should behave more or less the same!

Wildcard connections of parameters. It would've helped me today.

I know there is something I want having to do with clocking blocks... One second, I have to find it...
So I want some indication of when a clocking block updates a signal. See forum post for more information.

Here's the link to my question:
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=20576

Now onto Cadence:
PLEASE allow modports inside generate statements!

I know there is more, but I can't recall now sitting in front of the TV.