Xilinx once again fails bady when it comes to quality of tool issues. Recently I converted my PCI Express block from static to parametrized. This required lots arrays and multi-dimensional arrays, lots of parameters, and plenty of assign statements to take arrays out of and into modules (since module ports don't support multi-dimensional arrays). I implemented plenty of generate statements for conditional instantiation of FIFOs and also for loops for conditional processing of blocks.
The language specific way of breaking out of loops in Verilog is by using the "disable" statement. Sadly XST 11.1 doesn't support the disable statement from within a "for loop". The recommended workaround as shown in AR #22177 is to increment the "for loop" iterator to it's exit value. This works some of the time, and doesn't work other times. I stronly recommend against doing this as it clear to me that support for exiting a for loop early is shaky at best. I found that using a while statement with manual iteration worked better. I set the iterator to the exit value and it actually exited the loop properly.
Hoping that your experience is better than mine,