Friday, May 29, 2009

ISE 11.1 stability issues

I have been using ISE 11.1 for about a month now. There are numerous stability issues from crashes and freezes to messages no longer being updated in the Design Report view. I find that running Rerun All is always a crap shoot as it brings ISE down much of the time. I have gotten coregen to freeze on occasion when invoking it within the ISE project. ISE's tracking of source file states and build states is hit or miss. Sometimes it decides that Synthesis isn't up to date, but shockingly Map and P&R are. I change source files and it's completely unwilling to restart the process of compilation. This requires the infamous Rerun or Rerun All commands. Then it has those times when the compilation just won't work unless you "Cleanup Project Files" and then try again. I know that there are lots of temporary files being used during FPGA synthesis, and plenty of intermediate files created, but is it so difficult to check the state of the source files and if one has been updated recently to set build state back to zero?

These issues only strengthen the argument against ISE keeping an open handle to its configured external editor. See my post on problems when using an external editor from ISE.

Seems to me that Xilinx needs their GUI team updated.


  1. Hi,

    There is a better way to synthesize only the modified files. Go into the "implementation/" directory and delete both the library which is named after your VHDL source file module AND the filename in the cache library. After that, if you click on 'run' it will not syntheize the world again.

  2. Hi anon,
    I'm not sure what directory you are referring to. ISE 11.1 projects don't have an implementation folder from what I've seen. I am writing in Verilog for this application and perhaps the compilation system is different. Thanx for reading,

  3. What I can suggest is to open a WebCase or post the issue on Xilinx forum.
    I've done it many times and can attest that Xilinx does fix the problems.