Monday, July 6, 2009

ISE 11.2 and Partitions

Recently I thought to speed up my FPGA compilation times. One method of doing this is by using "Partitions." The idea behind a partition is that you mark a module or hierarchy of modules as a partition and that partition gets processed once and that's it. Unless of course you modify the partition in which case it is synthesized / mapped / placed and routed again.

Wouldn't it be nice if things worked as they were supposed to?

So partitions in ISE are going to be removed in version 12.1 and they will then only be available in PlanAhead. This means that Xilinx won't fix any of the many wonderful bugs in their partition implementation.

Two bugs that I've experienced with partitions:
1. Modify a source file that causes ISE's automated uninitiated parsing of source files to fail and all partition information may be removed. That depends on how badly the parsing failed. This sucks as ISE will parse your source files as soon as you set focus back onto ISE, and of course you may not be done editing your source files at that moment. (It should be noted that I use an external editor for my source files.)
2. INTERNAL_ERROR:Xst:cmain.c:3446:1.47.6.1 -
I don't know what this error is but it won't let my partitions work...

I've of course removed all partitions from the design.

hoping you have better experience with partitions
Posted by nachumk at 3:12 AM

6 comments:

  1. EvgeniJuly 6, 2009 at 1:51 PM

    I stopped using Partitions a while ago because it was too buggy. I found it did work only on very simple partitions, for example modules with small area and not too many interface signals.
    Anything more complex - memory controller, Xilinx PCI Express core, Ethernet MAC - would either fail or simply not work (even if the build was clean).

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  2. nachumkJuly 7, 2009 at 4:23 AM

    My first attempts at partitioning were complete failures as you can't partition a module that includes an Endpoint Block Plus for PCIe instance. Partitions are also problematic with MIGs if you have multiple MIGs with DQs in the same column. I separated my code to build partitions that got around all these issues, and still the whole partitioning system is buggy. As I said previously I no longer partition anything... it's a complete waste of time.

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  3. AmirJuly 24, 2009 at 12:19 PM

    I just got the same internal error after setting up partitions. Wouldn't it be great if FPGA tools didn't suck?

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  4. AnonymousAugust 7, 2009 at 2:17 AM

    Same error, no f... idea on how to fix it.
    Yes indeed, it would be great if they did not suck.

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  5. UnknownApril 22, 2010 at 4:23 AM

    Yet another good reason for using Altera FPGAs instead of Xilinx. In their synthesis tool "Quartus", partitions work perfectly :-).

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  6. nachumkApril 23, 2010 at 10:57 PM

    Ah, but Altera FPGAs don't include FIFO logic in their memory blocks, nor do they have distributed memory...
    And I enjoy the ability to instantiate Xilinx primitives directly without having to use wizards and other such things.
    I guess each vendor has their advantages and disadvantages.

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