Thursday, July 2, 2009

Using synchronous resets - delay them!

When I first started writing FPGAs some years back I was always shown how to use asynchronous resets. This reset line would have it's timing blocked, and it would be used throughout the FPGA. I have now become accustomed to using synchronous resets, and the first very obvious mistake I made was using a single reset line synchronously. This causes a huge and wasteful fanout. Register the reset line as it goes into different modules and you'll save yourself time when it comes to routing. It'll cost a few extra flip flops, but it's worth it. If your design can't deal with different modules coming out of reset at different times, then perhaps its time to rethink your design.


  1. There are app notes that explain why it's advantageous to use synchronous reset. They claim better logic utilization. In my experience, using async reset results in much faster MAP/PAR (in Xilinx FPGAs) comparing to synch reset, even with registered reset line.

  2. I have always had some problems with the ideas of async resets. The same thoughts as I was pondering were expressed very well in Xilinx's white paper:
    I won't bother repeating what the white paper says, but I can say that I feel much more secure and confident with my designs using synchronous resets.