Thursday, July 2, 2009
When I first started writing FPGAs some years back I was always shown how to use asynchronous resets. This reset line would have it's timing blocked, and it would be used throughout the FPGA. I have now become accustomed to using synchronous resets, and the first very obvious mistake I made was using a single reset line synchronously. This causes a huge and wasteful fanout. Register the reset line as it goes into different modules and you'll save yourself time when it comes to routing. It'll cost a few extra flip flops, but it's worth it. If your design can't deal with different modules coming out of reset at different times, then perhaps its time to rethink your design.
Posted by Nachum Kanovsky at 7:30 AM