Saturday, January 21, 2012

SystemVerilog, Cadence, Exporting a module task

I have recently been writing a lot of verification code with Cadence's tools. I use Incisive for RTL simulations. After using the tools for a while there are definitely limitations that are frustrating. But overall, the tools are very stable and support a large portion of SV, and support it really well. Kudos to Cadence for giving decent error messages on most occasions. That is really a huge plus even if the error is SV legal, but not yet supported.

Tip for calling tasks from a module using SV with Cadence's Incisive:
There are 2 ways, without using Verilog standard probing, to access tasks from within a module.
1. Create an interface. Declare a modport for the module with an exported task. Let the module define the exported task.
Cadence doesn't support this yet.
2. Create a class with the desired task declaration. Extend that class from within the module. Output an instance of the extended class for use elsewhere.
This method works fine with Cadence's tools.

Most people are satisfied with probing. In a small testbench, probing works OK. But when creating a large testbench with many identical modules (or modules with similar functionality), it is much nicer to have an array of class instances to work with. They lend themselves to more modular test designs.

About: System Verilog, Cadence Incisive, ncsim, ncvlog, export task, extends, exported tasks, extended classes, inherited classes, inheritance

1 comment:

  1. Is there any example or workaround to show the 2 way to call exported task in Cadence's tool