Saturday, February 4, 2012

SystemVerilog Classes and Parameters

I recently attempted to use an SV class with parameters. Simple parameters seem to work fine. You can templatize a class based on type or size. But that's about all you can do.

The limitations of how parameters work within a class are disappointing. As you may be aware, a parameter in a module or interface allows you the flexibility of generating different code for different parameter values. But as another example of the lack of uniformity throughout SystemVerilog they chose to not allow generate statements in a class. So the paramters look the same, but they can't be used the same way.

Another disappointment.

1 comment:

  1. I support your views on this non-uniformity of "parameter" keyword in System Verilog but usage for Classes is given here