Xilinx Divider IP and the Translate step

I have been building a highly optimized processing FPGA which requires amongst many other things a divider module. I used Core Generator to create the necessary divider. I have now noticed that the Translate step suddenly takes upwards of 2 hours to complete (with numerous dividers of course).... After lots of research and testcases it appears that Xilinx's divider module is very troublesome for their Translate tool (ngdbuild). This of course is extremely aggravating as the Translate is now the longest step by far in the whole compilation process.

I recently held a meeting with representatives of Synopsis regarding Synplify. I was happily surprised to see that they not only manage to decrypt the divider module, but to also write the divider directly into their output EDIF. The whole Synplify synthesis step took 30 minutes. This EDIF can then be Translated within a matter of minutes and of course mapped and routed. Amazing! Xilinx themselves spend over 2 hours during the Translate step which doesn't take into account XST time, whereas Synplify does the complete synthesis and bypasses the heavy Translate step in 30 minutes!!!

I am not impressed by Xilinx.

Perhaps someone knows of a Xilinx solution and would like to enlighten me.

To try this out on your own you need to create the largest divider you can and implement it a few times in a simple testcase. Easiest way is to connect the divider's ports directly to the I/O ports of the top module. The Translate step will be the longest step by far in the compilation process.