In attempting to compile a design at rates of 200 MHz or above I run into many timing issues with the MIG. Xilinx explains this because my board's pinout of the DDR2 pins are far away. I definitely agree with their analysis regarding why the MIG is failing to meet timing. What I don't understand is why Xilinx didn't add a parameter for increasing latency in order to increase the frequency. This is a trivial matter when dealing with a DDR2 controller.
Here's hoping MIG 3.2 will have such a parameter as this will be helpful for those occasions where you didn't place all the DDR2 pins where Xilinx believes they should be.
I guess I should delve into the MIG and add this parameter myself.... argh!