Tuesday, September 1, 2009

Xilinx Divider IP / Translate -- SOLUTION!!!

So I've spent a while studying this particular issue with the hope that I could puzzle out a solution. After a few hours I finally did. The issue is that the NGC that coregen creates is not flattened. The easiest way to fix this is to open the coregen-created NGC in PlanAhead, and let PlanAhead "Export Netlist". Take the exported .edf file and do a find replace to switch all "/" to "." (without quotes of course). This will flatten the netlist and the Translate step will now act nicely.

PS. This isn't a recommended solution for flattening other netlists, but it happens to be OK for the coregen dividers from what I can see. I didn't write a parser to verify legality or any such thing, so please don't complain if this doesn't work for you. And don't use this method for flattening other netlists!

I know there is at least one other person suffering with 12 hour translates and I hope he gets this information... I will pass this onto XilinxSupport and my FAEs and ask that they pass it on to you.

Perhaps this can save the next guy hours of wasted time

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