Quick review.... Licensing is the major change, and it was actually quite painless. Xilinx allows you to create licenses from the Entitlement page. My license was created immediately which in turn allowed me to start working immediately. Installation was done from the 5.3 GB tar file download also from Xilinx's Entitlement page. The download was fast, about 2 1/2 hours. Installation includes Chipscope, EDK and the standard ISE Foundation. The last step in the installation takes you to the licensing page and uploads your computer's ID so that the license can be created.
They have made some nice GUI improvements. The IDE looks smoother. They have also changed the text on many of the compilation messages. I'm guessing there was some overhauling done on all stages. Synthesis and par (Place and Route) are supposedly much faster. So far I haven't run into any major problems with the new tools. A nice change is the new xise project files. Finally a text based (XML) file that can easily be stored compared and modified.
There is a new MIG (Memory Interface Generator), version 3.0. The only difference I can see is that the previous requirements for column locations, and master / slave DQ bit information is no longer required. This is very nice as it means you can change IO constraints without having to run "Update Design," or manually change those values. Apparently this update is due to an update in the par which can intelligently place components without the previously required information. The other change in the MIG is that they are using PLLs now instead of DCMs. This might have to do with DCMs being removed from the Virtex 6, and to keep MIG compatible with the new chips.
Enjoy the new tools.