Xilinx I/O pin's location - left, right, or center?

So while working with the MIG (Memory Interface Generator) I was required to find out whether each DQS (Data Strobe) pin was located "Left", "Center", or "Right". I figured this should be easy, just open the documentation. It's not in the documentation. You can only find which bank a pin is in, but you can't find whether a bank (and all it's pins) are left, right or center. I finally discovered with the help of the FAE (Field Applications Engineer - support contact) that I can find whether a bank is left, right, or center by using the Floorplan view in the Floorpan Editor inside of ISE. When floating the mouse over I/Os you know which bank an I/O is in, and by the I/O's location you know whether that I/O and the others in the same bank are located left, right, or center. Another way to figure this out is by using the Package view in the Floorplan Editor and kinda seeing the groups of I/Os and where they are located on the package. Make sure to look at the top view so that the left I/Os are actually on the left instead of right, and vice versa.