SDRAM AL (Additive Latency)

So I've got to implement a SODIMM interface with Xilinx's MIG (Memory Interface Generator). One thing I've learned today is the very interesting use of the AL (Additive Latency) for SDRAM chips. Additive latency allows for commands to be issued to the SDRAM chip and have the SDRAM chip buffer the commands for AL (1,2,3,4, or 5) clocks depending on configuration. This is useful when the time between Activate (SDRAM command) and Read (SDRAM command) (tRCD) will cause a collision between the next Activate and the optimal clock for the Read to be issued on. See http://download.micron.com/pdf/technotes/ddr2/TN4710.pdf for a very good explanation of AL.